In the text Computer System Architecture (3rd Edition) by M Morris Mano , on pg. 415 under the section parallel priority interrupts I came across the following statements.
The bit in the interrupt register belonging to the source of the interrupt must be cleared so that it will be available again for the source to interrupt. The lower-priority bits in the mask register (including the bit of the source being interrupted) are set so they can enable the interrupt. The return to the interrupted program is accomplished by restoring the return address to PC. Note that the hardware must be designed so that no interrupts occur while executing steps 2 through 5; otherwise, the return address may be lost and the information in the mask and processor registers may be ambiguous if an interrupt is acknowledged while executing the operations in these steps. For this reason IEN is initially cleared and then set after the return address is transferred into PC.
My question is if an interrupt occurs again in the steps mentioned, why shall be the return address be lost? Could we just store the return address onto the stack as we have for handling a higher priority interrupt?
I could not understand how the information in the mask and processors might get ambiguous?
To understand the concepts better, here I include the entire detail of the context from the said text. It is a bit long, but please bear with me!!