For a while now, I have had issues understanding key aspects of the Northbridge-Southbridge architecture. The following are some of the questions I have asked, of which I have no answers as at the time of posting:
- What is the purpose of splitting functionality into two halves?
- What are the specific responsibilities of each half in relation to data transfer from device to CPU?
- How does this architecture handle concurrent data transfer requests? I there an internal buffer somewhere? Is data packetised for resource multiplexing?
- What kind of networking is used within both the Southbridge and Northbridge chips?
- What are the actual bottlenecks present in this architecture?
- How does this architecture handle the specific case of video streaming data from secondary storage to RAM?
I am aware of different chip manufactures, thus configurations, but I would appreciate any answer based on any architecture.