## usb – Is display MacBook Pro fuse or software protected against overpowered/ short circuit?

I did accidentally overpowered (12v) the USB Port of My MacBook Pro 2015 by putting a powered male usb. (I know that is stupid of me).
Immediately the display and the light of my keyboard went off.
I hear on the sound of the MacBook that the Mac is still alive.
Now I am questioning myself.
-are the display and keyboard light dead and have to be replaced?
-is there any protection mode designed by smart apple engineers to protect such a rare situation. By for example a fuse (for backlight/display, I found on YouTube the replacement instructions already. For keyboard I didn’t yet found any) or a software mode?

So, Any help, hint, instruction, link and or advice is welcome and very much Appreciated.

Thanks!

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## complexity theory – What is the comparator circuit?

The standard circuits $$AC^i$$, $$NC^i$$ are constructed using $$AND$$, $$OR$$ and $$NOT$$ of various fan-ins, fan-outs and depths.

What is the comparator gate constituted from?

Structurally why is it believed $$NC^i$$ is not in any $$CC^j$$ if $$igeq 1$$ and why is it believed $$CC^i$$ is not in any $$NC^j$$ if $$igeq 1$$ (refer https://arxiv.org/abs/1208.2721 for the conjecture $$NC$$ and $$CC$$ are incomparable)?

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## The datasheet says that USB operates on 1.8v instead of 3.3v, do I need some sort of logic level shifter in my circuit?

I’m trying to design a breakoutboard and connect the coral chip to my imx6 SoC vis usb. I’m assuming that the imx6 is using 3v3 logic because it doesn’t indicate otherwise and everything I’ve connected to it via usb thus far works fine. The data sheet of the Coral Edge TPU says that it operates on 1.8V. Do I need to account for this somehow in my design by assing a logic level shifter or something like that to my schematic? I don’t even really know if USB operates at 3.3v logic level either I’m just confused about why they would say that in the datasheet.

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## Upper bound for the size of a boolean circuit that computes a function \$f: {0,1}^n rightarrow {0,1}\$

I am trying to find an upper bound for the size of a boolean circuit of size $$s$$ that computes a function
$$f: {0,1}^n rightarrow {0,1}$$.

I believe an upper bound would be $$2s$$ since the usual convention is not to count “not” gates. Therefore, “not” gates can be pushed to immediately follow the input gates. So, ignoring “not” gates affects the size by at most $$n$$.

Im thinking of it intuitively but can someone point me to a more formal proof of this claim?

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## How can you convert the depth of a boolean circuit to its size?

I know that the depth of a circuit is the maximal length from an input gate to the output gate of the circuit and its size is its number of gates.

Is there a formula that you can go from depth to size and can someone explain the steps?

## algorithms – A person wants to connect n circuit points to the clock signal

A person wants to connect n circuit points to the clock signal. Now, the clock signal is going to pass parallel to the x-axis and all those circuit points are going to be connected by vertical to the clock line. Suppose the widths of the vertical wires in the given diagram also vary varying. If the coordinates($$x_i$$,$$y_i$$) for each circuit point $$c_i$$ to be connected are given, find y=$$y_c$$, through which the clock line should pass to minimize the expression PS: I don’t know latex that’s why I had to post snippets.

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## computer architecture – Changing the combinatorial circuit as little as possible to present correct prime numbers?

I’m very new to CS and I’ve been thinking long and hard about a certain problem of an exercise.

We are given a combinatorial circuit which is supposed to show prime numbers for y=1, however, it doesn’t work for the number 2, for 2 it’s y=0.

Here is the operator tree. https://ibb.co/bgGGQTP

And the combinatorial circuit: https://ibb.co/kSSP8hb

I’ve already constructed a new combinatorial circuit with minimal polynomial (making a draft for a new table, new dnf form, minimalising it, etc). The exercise states this is exactly what you are NOT supposed to do.
You are supposed to repair it, with as little change as possible.

So, I’ve tried to negate some conjunctions from the original DNF, and changing the AND3 gates to AND2 Gates to AND4 gates. etc, etc. None of this worked.

I’m getting crazy here, is there any easy solution I overlooked?

Any help would be really appreciated!
I’m very sorry for my bad English.
Thank you so much for reading.

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## complexity theory – Prove lower bound on boolean circuit

Given matrix $$A in {0,1}^{n times m}$$ with $$n$$ rows and $$m = 2^n – 1$$ columns. Where $$j$$-th column is binary decomposition of $$j$$ ($$j = 1 dots 2^n – 1$$). For example, if $$n = 3$$:

$$A = begin{pmatrix} 0 & 0 & 0 & 1 & 1 & 1 & 1 \ 0 & 1 & 1 &0 & 0& 1 & 1 \ 1 & 0 & 1 & 0 & 1 & 0 & 1 end{pmatrix}$$

This matrix calculates $$Ax$$ over $$({0,1}, oplus)$$, where $$x in {0,1}^m$$.

For example, if $$n = 3$$ it calculates $$(x_4 oplus x_5 oplus x_6 oplus x_7,; x_2 oplus x_3 oplus x_6 oplus x_7, ; x_1 oplus x_3 oplus x_5 oplus x_7)^T$$

This is a Boolean function with $$m = 2^n – 1$$ inputs and $$n$$ outputs. It can be represented by boolean circuit $$S$$ with $$m = 2^n – 1$$ inputs and $$n$$ outputs, where only XOR gates are allowed. Each XOR gate in circuit $$S$$ is binary — it takes exactly two inputs.

Let us denote by $$size(S)$$ number of gates in $$S$$ (we don’t count inputs as gates, but we count outputs as gates).

It is not hard to prove upper bound: $$size(S) le 2(2^n – 1 – n)$$.

Problem: Prove lower bound: $$size(S) ge 2(2^n – 1 – n)$$.

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## Telia price point 1G and 10G circuit

Hello,

can someone pvt me Telia current price brackets ?

## computer architecture – What is combinational circuit?

I’m reading the Digital Design and Computer Architecture by David Harris, Sarah Harris. The authors give the following definition of combinational logic:

A combinational circuit’s outputs depend only on the current values of
the inputs; in other words, it combines the current input values to
compute the output… A combinational circuit is memoryless, but a
sequential circuit has memory. The functional specification of a
combinational circuit expresses the output values in terms of the
current input values.

However, they claim this circuit is not combinational: because “node n6 connects to the output terminals of both I3 and I4”. Indeed, it’s one of the designated signs when a scheme can not be combinational but, according to the authors:

Certain circuits that disobey these rules are still combinational, so
long as the outputs depend only on the current values of the inputs.

As I’m able to catch on, the aforementioned circuit is the case: its output is 1 if and only if its inputs are both 1, otherwise the output is 0. So the output is defined as a function of the inputs (the AND function).

Circuit (d) cannot be written in this form (of formula), since the
outputs of I3 and I4 are wired together. What is the relation between
the input to the rightmost gate and the outputs of I3 and I4? Not
something that can be described combinatorially.

Unfortunately, I’m still confused due to

• The circuit, regarded as a black box, is still in scope of the combinational logic definition: its output values depend only on the current values of the inputs;
• The relation between the input to the rightmost gate and the outputs of I3 and I4 can be described through the function NAND of the circuit inputs and this function is quite “memoryless”. It’s not obvious for me why we can’t afford to depict a gate input using multiple outputs of other gates.

I need some elaboration. Maybe things would fall into place if someone provide a circuit example when two gates outputs is connected to one input and it actually causes “memory” (in contrast to the considered sample).

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