cpu – Understanding the intel-rapl in Linux

Here is the rapl interface tree provided by a Ubuntu system running on Intel I5-7200U.

├── enabled
├── intel-rapl:0
│   ├── constraint_0_max_power_uw
│   ├── constraint_0_name
│   ├── constraint_0_power_limit_uw
│   ├── constraint_0_time_window_us
│   ├── constraint_1_max_power_uw
│   ├── constraint_1_name
│   ├── constraint_1_power_limit_uw
│   ├── constraint_1_time_window_us
│   ├── device -> ../../intel-rapl
│   ├── enabled
│   ├── energy_uj
│   ├── intel-rapl:0:0
│   │   ├── constraint_0_max_power_uw
│   │   ├── constraint_0_name
│   │   ├── constraint_0_power_limit_uw
│   │   ├── constraint_0_time_window_us
│   │   ├── device -> ../../intel-rapl:0
│   │   ├── enabled
│   │   ├── energy_uj
│   │   ├── max_energy_range_uj
│   │   ├── name
│   │   ├── power
│   │   │   ├── async
│   │   │   ├── autosuspend_delay_ms
│   │   │   ├── control
│   │   │   ├── runtime_active_kids
│   │   │   ├── runtime_active_time
│   │   │   ├── runtime_enabled
│   │   │   ├── runtime_status
│   │   │   ├── runtime_suspended_time
│   │   │   └── runtime_usage
│   │   ├── subsystem -> ../../../../../../class/powercap
│   │   └── uevent
│   ├── intel-rapl:0:1
│   │   ├── constraint_0_max_power_uw
│   │   ├── constraint_0_name
│   │   ├── constraint_0_power_limit_uw
│   │   ├── constraint_0_time_window_us
│   │   ├── device -> ../../intel-rapl:0
│   │   ├── enabled
│   │   ├── energy_uj
│   │   ├── max_energy_range_uj
│   │   ├── name
│   │   ├── power
│   │   │   ├── async
│   │   │   ├── autosuspend_delay_ms
│   │   │   ├── control
│   │   │   ├── runtime_active_kids
│   │   │   ├── runtime_active_time
│   │   │   ├── runtime_enabled
│   │   │   ├── runtime_status
│   │   │   ├── runtime_suspended_time
│   │   │   └── runtime_usage
│   │   ├── subsystem -> ../../../../../../class/powercap
│   │   └── uevent
│   ├── intel-rapl:0:2
│   │   ├── constraint_0_max_power_uw
│   │   ├── constraint_0_name
│   │   ├── constraint_0_power_limit_uw
│   │   ├── constraint_0_time_window_us
│   │   ├── device -> ../../intel-rapl:0
│   │   ├── enabled
│   │   ├── energy_uj
│   │   ├── max_energy_range_uj
│   │   ├── name
│   │   ├── power
│   │   │   ├── async
│   │   │   ├── autosuspend_delay_ms
│   │   │   ├── control
│   │   │   ├── runtime_active_kids
│   │   │   ├── runtime_active_time
│   │   │   ├── runtime_enabled
│   │   │   ├── runtime_status
│   │   │   ├── runtime_suspended_time
│   │   │   └── runtime_usage
│   │   ├── subsystem -> ../../../../../../class/powercap
│   │   └── uevent
│   ├── max_energy_range_uj
│   ├── name
│   ├── power
│   │   ├── async
│   │   ├── autosuspend_delay_ms
│   │   ├── control
│   │   ├── runtime_active_kids
│   │   ├── runtime_active_time
│   │   ├── runtime_enabled
│   │   ├── runtime_status
│   │   ├── runtime_suspended_time
│   │   └── runtime_usage
│   ├── subsystem -> ../../../../../class/powercap
│   └── uevent
├── intel-rapl:1
│   ├── constraint_0_max_power_uw
│   ├── constraint_0_name
│   ├── constraint_0_power_limit_uw
│   ├── constraint_0_time_window_us
│   ├── constraint_1_max_power_uw
│   ├── constraint_1_name
│   ├── constraint_1_power_limit_uw
│   ├── constraint_1_time_window_us
│   ├── device -> ../../intel-rapl
│   ├── enabled
│   ├── energy_uj
│   ├── max_energy_range_uj
│   ├── name
│   ├── power
│   │   ├── async
│   │   ├── autosuspend_delay_ms
│   │   ├── control
│   │   ├── runtime_active_kids
│   │   ├── runtime_active_time
│   │   ├── runtime_enabled
│   │   ├── runtime_status
│   │   ├── runtime_suspended_time
│   │   └── runtime_usage
│   ├── subsystem -> ../../../../../class/powercap
│   └── uevent
├── power
│   ├── async
│   ├── autosuspend_delay_ms
│   ├── control
│   ├── runtime_active_kids
│   ├── runtime_active_time
│   ├── runtime_enabled
│   ├── runtime_status
│   ├── runtime_suspended_time
│   └── runtime_usage
├── subsystem -> ../../../../class/powercap
└── uevent

Accordding to Power Capping Framework, this system contains two CPU packages intel-rapl:0 and intel-rapl:1. However, different from intel-rapl:0, intel-rapl:1 doesn’t have subfolders representing core part(intel-rapl:0:0) and uncore part(intel-rapl:0:1), which gives me a feeling that this is not a real package. Meanwhile intel-rapl:1 still have file interface energy_uj showing that it’s consuming energy.

So how should I understand this situation, is intel-rapl:1 a complete package? If so, why are files missing?

Migrating to server with much fewer CPU cores

We are in process of migration from our legacy SQL servers hosted on 2014 version to 2019.

Currently the no. of logical cores provided on physical host is 64 and we’ve been asked to migrate these applications to VMs but to much less cores. Proposed is 40 , though RAM they are provisioning is 800 GB on VMs where physical is 400 but CPUs are just chopped to almost half.

Its been confirmed that these cores are going to be CPU on faster clock cycle speed compared to physical which as per me seem good for app which have more of the load running serially. Please correct if my understanding is not correct here?

However I do see a concern with MAX worker threads that come on physical as 1472 and gets reduced on VM to 1088.

Current usage of CPU is avg 30%

Avg Batch req/sec is 5000

Avg max worker threads when monitored over month is 800. However the catch is during peak load time there are spikes beyond 1472 and goes around 1800. I do not understand how max can it go before it might do a node failover or SQL restart as i have seen on few due to THREADPOOL waits. My second question would be is this really a concern if lets say we have an hour of peak time with those many threads in morning and same spike in an hour in night? I do see option to increase the MAX worker threads but lot on web says not to touch that button. Please suggest how big could this be a problem?

Batch re/sec on above 2 hours of spike to 35K , while rest of day its just under 5K.

Any idea on how to deal this situation and if there is actually a solution to this because requesting additional hardware as of now is no go.

Much appreciate , thanks!

macos – Kernel_task uses 15% of CPU, but stops as soon as the computer is used? (10.15.7, Mid 2012 15″ Retina MBP)

I have a 15″ Mid 2012 Retina MacBook Pro (2.7ghz i7, 16gb of RAM) that I use as a headless server in my house. It’s currently running 10.15.7, which is the last supported MacOS release it can run.

When I leave the machine running, screen open but brightness all the way down, the fan CONSTANTLY runs. As soon as I turn the brightness up and start using the computer, or remote in with a VNC client (I’m using the one that’s an extension for chrome) the fan stops running. Looking at Activity monitor, there’s a kernel_task that using around 15% of the CPU that immediately stops when I remote in or start using the computer. You can see the task and drop in CPU usage in the attached screenshot (screenshot taken after the %CPU has dropped, but you can see kernel_task, and the associated load on the graph at the bottom).

I’ve done a clean install of 10.15.7, and the only programs I have installed are: Chrome, Docker, pi-hole running in Docker, and Homebridge (for homekit).

I thought it might just be spotlight re-indexing the computer, but it’s been about a week and the problem hasn’t gone away. I have tried a SMC and PRAM reset, and neither have helped. It’s pretty much running a clean install, other than the programs I have listed.

Does anyone have any tips for figuring out what is causing kernel_task to use the CPU so often? Why does it go away when I start using the computer?

enter image description here

Server Trafficweb :- 2x Intel Xeon CPU | 8 User MAX | 64 GB RAM | 1 Gbps Full Duplex | Admin Encoding RDP | Storage RDP

Live Chat:- https://www.servertrafficweb.com/
Contact Us:- contact@servertrafficweb.com
Stay Connected with Skype:-
live: servertrafficweb

{
“lightbox_close”: “Close”,
“lightbox_next”: “Next”,
“lightbox_previous”: “Previous”,
“lightbox_error”: “The requested content cannot be loaded. Please try again later.”,
“lightbox_start_slideshow”: “Start slideshow”,
“lightbox_stop_slideshow”: “Stop slideshow”,
“lightbox_full_screen”: “Full screen”,
“lightbox_thumbnails”: “Thumbnails”,
“lightbox_download”: “Download”,
“lightbox_share”: “Share”,
“lightbox_zoom”: “Zoom”,
“lightbox_new_window”: “New window”,
“lightbox_toggle_sidebar”: “Toggle sidebar”
}

FVgsoId.jpg



Live Chat:- https://www.servertrafficweb.com/
Contact Us:- (COLOR=rgb(65…(/B)

Read more

Find how many instructions must be executed so a CPU runs faster than another one (Computer Architecture)

Suppose we have 2 different CPUs, C1 and C2. C1 is clocked at 2,5ghZ, and C2 is clocked at 3ghZ. In each CPU there can only be 2 categories of instructions. For C1, the instructions in Category 1 need 2 clocks to be executed, and the instructions in Category 2, need 3 clocks to be executed. For C2, the instructions in Category 1 need 4 clocks to be executed, and the instructions in Category 2, need 1 clocks to be executed. If the program that is being tested in both CPUs is 3 billion instructions long, and X% are the instructions executed in Category 1, find the X such that C1 is faster than C2.

My try:

First of all I want to find the X% such that C1 is faster than C2, so this is equivalent to $$frac{text{C1 CPU time}}{text{C2 CPU time}}geq 1$$

We know that the C1 CPU time is equal tο the clocks by the rate of the CPU, but the clocks are equal to the plurality of the instructions time the CPI

Let x be the number of instructions that are of type 1, then all the other will be at the other category, so we have x instructions in Category 1, and (3 billion- x) instructions in Category 2.

So:

$$text{C1 CPU time} = frac{2x+3(3 cdot 10^9-x)}{2,5ghZ}$$ and

$$text{C2 CPU time} = frac{4x+(3 cdot 10^9-x)}{3ghZ}$$
From the above: $$frac{frac{2x+3(3 cdot 10^9-x)}{2,5ghZ}}{frac{4x+(3 cdot 10^9-x)}{3ghZ}} geq 1 Rightarrow frac{3 cdot ( 2x+3(3 cdot 10^9-x) )}{2,5 cdot (4x+(3 cdot 10^9-x))} geq 1 Rightarrow dots Rightarrow-6x + 54 cdot 10^9 geq 15x + 15cdot 10^9 Rightarrow x% leq frac{39}{21}cdot10^7$$

However I am given 4 choices that none of them match it (Namely: (1) At least 61.91% (2) At least 51.22%, (3) At most 45,50%, (4) At most 17.31%)). What am I doing wrong here? Thanks

assembly – What will a given CPU architecture do in the event that we were to invert all of the instruction bits to a given instruction?

Given an arbitrary CPU – Architecture and its instruction set… What would be the outcome of the given inverted instruction within that Architect?

For simplicity, let’s use an 8-bit CPU architecture that has an 8-bit Bus design where that bus is used for both addressing and data transfer operations. A single instruction or micro instruction will act on an 8-bit string of binary digits per clock cycle. Each clock cycle may consist of 3,4,or 5 micro instructions before incrementing the instruction register for the next full instruction to be processed. These would account for the Fetch, Decode, and Execute phases of a single CPU clock cycle instruction.

The following is a mock-up only to demonstrate or illustrate my curiosity and concern while designing the layout of a given ISA(Instruction Set Architecture)…

Here we have the range of possible instructions from (0000 0000, 1111 1111) which are all of the possible permutations that this arbitrary CPU-Architecture’s Machine Language can support. We could use Ben Eater’s 8-bit Bread Board CPU and its ISA as an example… You can find that here along with other useful videos from his YouTube channel: Comparing C to Machine Language, and Programming 8-Bit Computer. With his given implementation, the first 4 bits are used to define the instruction and the second 4 bits are used for data {either memory address or immediate value}…

Now to my question: Given a specific instruction word and its accompanying data field, what would be the resulting outcome if we invert all of the instruction bits?

First, I know that this would be independent on each Architecture’s ISA design implementation… Second, I’m just curious to what the ramifications would be when designing your own specifications in that, would it be possible to carefully design and layout your bit fields per instruction in a manner that you could have a special invert operation, that would automatically invert a given instruction where that inversion would produce the opposite or inverse effect of the given incoming instruction? Now, the inversion won’t necessarily happen to the entire instruction string that includes all 8-bits, but only to the bit-fields that pertain to the instruction type while preserving the data field… For example:

  • If we have an Add instruction, the invert op would turn this to a Sub…
  • If we have an And instruction, the invert op would turn this to an Or instruction…
  • If we have either a Bit Shift Logical Left or Bit Shift Arithmetic Left, the invert op
    would respectively turn these into Bit Shift Logical/Arithmetic Right operations…
  • And so on…

Would such a design be possible to have perfect symmetry within it’s ISA?

-Note- I don’t know if this is the correct StackExchange site for this question… if it is not please don’t down vote it due to being irrelevant and be kind enough to point me in the right direction letting me know where the appropriate site for this question would be.

windows 10 – Hibernate after 10 minutes of inactivity regardless of CPU Usage?

In Windows 10, I can set up the PC to hibernate after certain time of inactivity using Task Scheduler.
But this works when the CPU usage is under certain criterion: this is how Windows 10 defines inactivity.
Can I hibernate PC after certain time (such as 15 minutes) of inactivity regardless of CPU or RAM usage?
What I mean is to determine ‘inactivity’ solely by keyboard or mouse input.

vmware esxi – Windows 2016 Server VM – dialogs in various apps are displayed after tens of seconds when CPU usage is around 20%-30%

This issue baffles me.

I’ve been given a Windows 2016 Server VM to do development on. The specs for the VM are:

Hypervisor: VMware ESXi, 6.5.0, 13004031
Model: ProLiant BL460c Gen8
Processor Type: Intel (R) Xeon(R) CPU E5-2560 0 @2.00GHz

Specs from the Windows system information:
OS Name Microsoft Windows Server 2016 Standard
Version 10.0.14393 Build 14393
Other OS Description    Not Available
OS Manufacturer Microsoft Corporation
System Manufacturer VMware, Inc.
System Model    VMware Virtual Platform
System Type x64-based PC
System SKU  
Processor   Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz, 2000 Mhz, 1 Core(s), 1 Logical Processor(s)
Processor   Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz, 2000 Mhz, 1 Core(s), 1 Logical Processor(s)
Processor   Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz, 2000 Mhz, 1 Core(s), 1 Logical Processor(s)
Processor   Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz, 2000 Mhz, 1 Core(s), 1 Logical Processor(s)
Processor   Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz, 2000 Mhz, 1 Core(s), 1 Logical Processor(s)
Processor   Intel(R) Xeon(R) CPU E5-2650 0 @ 2.00GHz, 2000 Mhz, 1 Core(s), 1 Logical Processor(s)
BIOS Version/Date   Phoenix Technologies LTD 6.00, 9/19/2018
SMBIOS Version  2.4

The problem that I have is that sometimes dialogs in various applications, usually written in Delphi or Visual C++ take a long time to show up when the CPU usage is around 20%-30%.

I am using Toad Data Modeler (TDM – written in Delphi), The Journal (written in Delphi) and SAP Power Designer (PD – written probably in VC++).

When I click on a table to display the table properties, for instance, in a TDM model (this brings a dialog with lots of tabs), it can take up to 20s for the dialog to show up. In the Journal I had some weird experience where I was typing letters and they would show up one by one in slow motion. Today, I have the same issue with PD. The common pattern when I experience this slowness is a current CPU background usage of somewhere between 20 and 30%. I started to close apps and I got the CPU humming below 10% and the dialogs show up much faster.

I compared this to my Windows 10 VM running on a MBP 16″ (inside Desktop Parallels), and it is incomparable. My VM is much faster. I used the same TDM model to test, and I even have fewer cores assigned.

Any ideas? I know it’s not much information to go on, but I hope that someone with the knowledge of VMs and Windows internals has at least a theory. To me it looks like the dialogs are processed on a core that is (CPU) starved, even though the VM has been assigned 6 cores.

Thanks